1. Field of the Invention
Embodiments relate to a semiconductor device and a method of generating voltages using the same and, more particularly to generation of voltages with various levels.
2. Description of the Related Art
NAND memory cells of semiconductor memory have an erase state or program states according to levels of threshold voltages. More particularly, a memory cell programmed with one level of threshold voltage is called a single level cell (hereinafter referred to as an ‘SLC’), and a cell programmed with various levels of threshold voltages is called a multi-level cell (hereinafter referred to as an ‘MLC’).
Active research has recently been done on the MLC because the MCL typically has more capacity as compared with the SLC. In general, the MLC has one erase state and three program states, but a cell having one erase state and three or more program states is being developed.
FIG. 1 is a graph illustrating threshold voltage distributions of memory cells.
Memory cells having one erase state ER and seven program states PV1 to PV7 are described as an example with reference to FIG. 1. In order for memory cells to have seven program states as described above, seven program verification voltages Vf1 to Vf7 are required. In order to perform a read operation after the program routine, seven read voltages Vr1 to Vr7 are required.
That is, the number of voltage levels to be generated is increased in proportion to the number of program states. For example, in a semiconductor device having three program states, data of 8 bits is used in order to determine voltage levels. When data of 8 bits (that is, control bits) are used, 256 (2^8=256) voltages of different levels may have to be generated. Accordingly, voltage levels necessary for a program operation, a read operation, a verification operation, and an erase operation can be generated. However, with an increase in the number of program states, voltages of more various levels need to be generated with more accurate differences between levels.